Nanoelectromechnical systems (NEMS) are seen as one of the most promising candidates for next generation extreme low power electronics that can operate as a versatile switch/memory/sensor/display element. The NEMS devices have often been mentioned as one of the most promising candidates in ITRS roadmap for a number of emerging device categories. The effective zero standby power dissipation and low subthreshold swing make it an ideal candidate for a logic switch (NEMFET), its intrinsic hysteresis suggests potential as a non-volatile memory element (NEMM), and its high quality factor and sensitivity to changes in mass/stiffness promise applications as RF resonators or nanobiosensors.
One of the main challenges toward this goal lies in the fabrication difficulties of ultra-scaled NEMS which is required for high density integrated circuits. It is believed that fabricating and operating a NEMS with an airgap below a few nanometers will be extremely challenging due to factors including surface roughness, non-ideal forces and tunneling. A Micro/Nano electromechanical system (M/NEMS) consists of a pair of electrodes—one fixed and the other movable—separated by an airgap. However, the most difficult challenge inhibiting the integration of these devices in next generation chips has been the reliable scalability of NEMS devices. For example, a low power memory/switch requires sub-1V actuation (VPI), which can be achieved only if the airgap is scaled to a few nanometer range. Such an extreme scaling poses a difficult fabrication challenge. Moreover, the reduced airgap leads to the introduction of many non-ideal physical effects, such as the tunneling current (for less than 2 nm) which in turn degrades the subtreshold swing (SS) and standby power dissipation, the surface forces (for example, Van der Wall and Casimir) causing stiction, etc. Therefore, although NEMS switches with a 4 nm airgap (sub-1V VPI) using a pipe-clip structure have been reported, the most advanced devices based on conventional geometry rely on an airgap of 15 nm (with a corresponding pull-in voltage, VPI=13V).
Ferroelectric (FE) negative capacitors are known. Recently, Salahuddin and Datta has reported a ferroelectric negative capacitor connected in series with a classical gate oxide transistor in which the gate voltage was amplified and thereby reduced the sub-threshold swing below the 60 mV/decade limit. It is well-known that an FE capacitor is characterized by a negative capacitance around zero charge, but the capacitor—by itself—cannot be operated at this unstable point. Operation of an FE capacitor around this negative capacitance regime is possible only if the overall system is stabilized by adding a series capacitor. The stability comes from the fact that the charge state of the combined structure is determined by, not the FE alone, but the energetics of the overall structure. An elementary circuit analysis shows that, in the negative capacitance regime, the voltage across the FE capacitor can also be negative, even when a positive voltage is applied across the combined structure. Since the total applied voltage is constant, therefore, the voltage across the remaining series capacitor is higher than the applied voltage. Such voltage amplification is the basis of sub-60 mV/decade operation of the negative capacitance field effect transistor (NCFET) where the gate stack contains the FE film, and the remaining gate and the channel capacitance act as the series capacitor that stabilizes the FE film.
Another problem involves switches, which are the most basic component of integrated circuit (IC) technology. The sub-threshold swing (S) characterizes the switching characteristics of a switch where S=0 mV/decade corresponds to an ideal switch. However, current IC technology relies on field effect transistors (FETs) which are non-ideal in practice. The switching characteristics of a classical FET are far from being ideal and thermodynamics dictate that S cannot be lower than 60 mV/decade. Alternative approaches using devices with gate insulators with negative capacitance (NC) that have S<60 mV/decade such as Ferroelectric-FETs and suspended gate FETs have been developed. However, these approaches have not been able to achieve an ideal switching characteristic of S=0 mV/decade. Moreover, existing approaches of 0 mV/decade are not hysteresis-free. Therefore, improvements are needed in the field.